1. Field of the Invention
This invention relates to latch, driver and clocking circuits in CMOS technology, and more particularly to such circuits and clocking sequences therefor which control master latch and slave latch circuits to facilitate at-speed testing and operation.
2. Description of the Related Art
Computational systems are composed of a collection of circuitry that may be either sequential or combinational in nature. A sequential circuit is one whose output logic state is dependent upon a prior event, an input and a time coincident clocking pulse. The output of a sequential circuit usually remains constant until the next sequence of clocks is applied to the circuit. In contrast, a combinational circuit is one whose output depends solely upon the state of the data inputs and the logical function of the circuitry, independent of time. The output of a combinatorial circuit will only remain stable while the input signals to that circuit remain unchanged.
Computation systems commonly include numerous latches that operate in selected sequences during recurring clock intervals to capture and hold certain data for a period of time sufficient for the other circuits within the system to further process that data. At each clock signal, data is stored in a set of latches whose outputs are available to be applied as inputs to other combinatorial or sequential circuitry during successive clock signals. In this manner, sequential logic circuits are operated to capture, store, and transfer data during the successive clock signals.
Certain known latch circuits operate as scannable latches that can be assembled as shift registers to shift data in as well as to shift data out under the control of applied clock signals. In response to proper control signals, such scannable latches can be interrupted from normal operation to shift out existing data for examination, or to shift in test data for further processing to yield test results. Scannable latches of this type are described in the literature (see, for example, U.S. Pat. No. 4,495,629).
Faulty circuitry can be readily isolated through the use of scannable latches. Faulty circuitry is caused by the failure of a particular circuit element to perform the correct logical operation or by a timing fault. The former type of fault is called a static fault and is readily detectable using the normal scan test techniques of the prior art. Timing faults, on the other hand, occur when the combinatorial logic elements fail to perform their function within the minimum time period specified by the system clock interval. Time dependent faults are not easily detected using the scan testing techniques because they often require testing the circuit in question at a clock period equivalent to the minimum clock period specified by the original design parameters. Such testing is called "at-speed" testing.
At-speed testing may be further complicated due to the complexity of the circuit in question, and the interconnecting logic to the input latches of that circuit. To be fully efficient, an at-speed testing technique must permit control of all the inputs and observation of all the outputs of the combinatorial section of logic to be tested. Furthermore, such at-speed technique must be capable of providing a logical transition at each of the inputs and a means of observing the resulting circuit transition on the output. Current scan testing techniques do not provide this capability.